This invention relates to nonvolatile memories and in particular, the use of redundant data storage units in flash memories to replace defective data storage units.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which employ an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells formed on one or more integrated circuit chips. A memory controller, usually but not necessarily on a separate integrated circuit chip, interfaces with a host to which the card is removably connected and controls operation of the memory array within the card. Such a controller typically includes a microprocessor, some non-volatile read-only-memory (ROM), a volatile random-access-memory (RAM) and one or more special circuits such as one that calculates an error-correction-code (ECC) from data as they pass through the controller during the programming and reading of data. Some of the commercially available cards are CompactFlash™ (CF) cards, MultiMedia cards (MMC), Secure Digital (SD) cards, Smart Media cards, personnel tags (P-Tag) and Memory Stick cards. Hosts include personal computers, notebook computers, personal digital assistants (PDAs), various data communication devices, digital cameras, cellular telephones, portable audio players, automobile sound systems, and similar types of equipment. Besides the memory card implementation, this type of memory can alternatively be embedded into various types of host systems.
Two general memory array architectures have found commercial application, NOR and NAND. In a typical NOR array, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,313,421, 5,315,541, 5,343,063, 5,661,053 and 6,222,762. These patents, along with all other patents, patent applications and other publications cited in this application are hereby incorporated by reference in their entirety.
The NAND array utilizes series strings of more than two memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, and 6,522,580.
The charge storage elements of current flash EEPROM arrays, as discussed in the foregoing referenced patents, are most commonly electrically conductive floating gates, typically formed from conductively doped polysilicon material. An alternate type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of the conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (ONO) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region, and erased by injecting hot holes into the nitride. Several specific cell structures and arrays employing dielectric storage elements and are described in U.S. patent application Publication No. 2003/0109093 of Harari et al.
As in most integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit functions also exists with flash EEPROM memory arrays. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell and/or per storage unit or element. This is accomplished by dividing a window of a storage element charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores three bits of data per storage element, and so on. Multiple state flash EEPROM structures using floating gates and their operation are described in U.S. Pat. Nos. 5,043,940 and 5,172,338, and for structures using dielectric floating gates in aforementioned U.S. patent application Publication No. 2003/0109093. Selected portions of a multi-state memory array may also be operated in two states (binary) for various reasons, in a manner described in U.S. Pat. Nos. 5,930,167 and 6,456,528.
Memory cells of a typical flash EEPROM array are divided into discrete blocks of cells that are erased together. That is, the block is the erase unit, a minimum number of cells that are simultaneously erasable. Each block typically stores one or more pages of data, the page being the minimum unit of programming and reading, although more than one page may be programmed or read in parallel in different sub-arrays or planes. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system. An example sector includes 512 bytes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the block in which they are stored. Such memories are typically configured with many pages in each block, and each page storing multiple host sectors of data.
In order to increase the degree of parallelism during programming user data into the memory array and read user data from it, the array is typically divided into sub-arrays, commonly referred to as planes, which contain their own data registers and other circuits to allow parallel operation such that sectors of data may be programmed to or read from each of several or all the planes simultaneously. An array on a single integrated circuit may be physically divided into planes, or each plane may be formed from a separate one or more integrated circuit chips. Examples of such a memory implementation are described in U.S. Pat. Nos. 5,798,968 and 5,890,192.
To further efficiently manage the memory, blocks may be linked together to form virtual blocks or metablocks. That is, each metablock is defined to include one block from each plane. Use of the metablock is described in U.S. Pat. No. 6,763,424 which patent is hereby incorporated by reference in its entirety. The metablock is identified by a host logical block address as a destination for programming and reading data. Similarly, all blocks of a metablock are erased together. The controller in a memory system operated with such large blocks and/or metablocks performs a number of functions including the translation between logical block addresses (LBAs) received from a host, and physical block numbers (PBNs) within the memory array. Individual pages within the blocks are typically identified by offsets within the block address. Address translation often involves use of intermediate terms of a logical block number (LBN) and logical page.
In some memory systems, the physical memory cells are also grouped into two or more zones. A zone may be any partitioned subset of the physical memory or memory system into which a specified range of logical block addresses is mapped. For example, a memory system capable of storing 64 Megabytes of data may be partitioned into four zones that store 16 Megabytes of data per zone. The range of logical block addresses is then also divided into four groups, one group being assigned to the physical blocks of each of the four zones. Logical block addresses are constrained, in a typical implementation, such that the data of each are never written outside of a single physical zone into which the logical block addresses are mapped. In a memory array divided into planes (sub-arrays), which each have their own addressing, programming and reading circuits, each zone preferably includes blocks from multiple planes, typically the same number of blocks from each of the planes. Zones are primarily used to simplify address management such as logical to physical translation, resulting in smaller translation tables, less RAM memory needed to hold these tables, and faster access times to address the currently active region of memory, but because of their restrictive nature can result in less than optimum wear leveling.
Individual flash EEPROM cells store an amount of charge in a charge storage element or unit that is representative of one or more bits of data. The charge level of a storage element controls the threshold voltage (commonly referenced as VT) of its memory cell, which is used as a basis of reading the storage state of the cell. A threshold voltage window is commonly divided into a number of ranges, one for each of the two or more storage states of the memory cell. In this way, a cell can hold one bit of data or can hold two or more bits of data depending on the number of voltage ranges. These ranges are separated by guardbands that include a nominal sensing level that allows determining the storage states of the individual cells. These storage levels often shift as a result of charge disturbing programming, reading or erasing operations performed in neighboring or other related memory cells, pages or blocks. Error correcting codes (ECCs) are therefore typically calculated by the controller and stored along with the host data being programmed and used during reading to verify the data and perform some level of data correction if necessary. Also, shifting charge levels can be restored back to the centers of their state ranges from time-to-time, before disturbing operations cause them to shift completely out of their defined ranges and thus cause erroneous data to be read. This process, termed data refresh or scrub, is described in U.S. Pat. Nos. 5,532,962 and 5,909,449, which patents are hereby incorporated by reference in their entirety.
Memory cells in a memory array may sometimes be defective. Cells may be defective in a new memory chip because of a manufacturing defect or may become defective during use of the chip. Where a cell become defective during use, the defect may be detected by failure to erase, write to or read from the cell. One way to deal with such defects is to store data that would be stored in a defective portion of the memory at another location. Such remapping of data from a defective location to a replacement location is described in U.S. Pat. No. 5,535,328, entitled “Non-volatile memory system card with flash erasable sectors of EEPROM cells including a mechanism for substituting defective cells,” which patent is hereby incorporated by reference in its entirety. The defective cell may be remapped to a different location or an entire sector may be remapped to another location. Another scheme for relocating data away from defective cells is described in U.S. Pat. No. 5,200,959, entitled “Device and method for defect handling in semi-conductor memory,” which patent is hereby incorporated by reference in its entirety. The data of an entire block may also be relocated in this way when a defective cell is found in one block of the memory array.
Yet another scheme for managing defective cells is described in U.S. Pat. No. 5,438,573, entitled “Flash EEPROM array data and header file structure,” which patent is hereby incorporated by reference in its entirety. This scheme relocates a bit of data corresponding to a defective memory cell to the next cell in the row. The bit corresponding to the next cell is relocated to its neighbor and so on, so that the bits in the row are pushed over by one bit. Redundant bits are provided in each row so that the data still fits in the row.
Defective cells may be detected in several ways either during a testing procedure, typically done at the factory prior to use of the memory chip by a user, or during normal use where defects are generally found by the memory controller. Factory testing generally finds physical defects resulting from manufacturing. Such testing uses dedicated test equipment that is connected to the memory system for testing but is disconnected after testing is complete. The defective area is remapped in a permanent manner. Defects may be found by attempting to program, read and erase portions of the memory array to see if any cells fail to perform within specified limits. Latent defects may also be detected as described in U.S. Pat. No. 5,428,621, entitled “Latent defect handling in EEPROM devices,” which patent is hereby incorporated by reference in its entirety.
In some prior art designs, redundant columns of cells are provided to replace defective columns in the memory array. Such redundant columns do not store any data if there are no defects in the memory array. FIG. 1 shows an example of the use of redundant columns according to the prior art. During testing of a memory array, it is found that a memory cell is defective. The defect may be the result of contamination, misprocessing or some other cause. When defective cell 101 is encountered in column 1, column 1 is considered defective and is mapped to redundant column A. This mapping is recorded in some way so that column 1 is not used. Typically, the mapping is recorded by burning fuses that indicate the column that is defective. Any data that would have been sent to column 1 if it were not for the remapping is now sent to redundant column A. Defective cell 101 is replaced by replacement cell 103. In addition, all the other cells of column 1, which are not defective, are also replaced by cells in redundant column A.
FIG. 2 shows a simplified illustration of a memory system 200 for carrying out column replacement illustrated in FIG. 1. During testing, a flash fuse is burned to indicate the location of a defective column. A flash fuse is a flash cell or group of cells that is treated as a fuse, but unlike conventional fuses may be reprogrammable. There may be one fuse for each non-redundant column of flash memory cell array 221. When memory system 200 starts up, flash fuses 220 are read into column redundancy control registers 222 so that the location of the defective column and its replacement are indicated by the contents of the registers. When the host sends a memory access command, the physical address to be accessed is compared with the column addresses in column redundancy control registers 222. If a defective column is indicated, then instead of trying to access the defective column, the replacement column is accessed. Thus, column redundancy control registers 222 provide a replacement column address to Y-address decode circuitry 224 so that the defective column is not accessed. More than one defective column may be replaced in this way. Typically, a number of replacement columns 226 are provided so that a number of columns may be replaced. FIG. 1 shows N+1 non-redundant columns (columns 0 to N) and four redundant columns (columns A to D). Word lines extend across the array at right angles to the columns, extending over both redundant and non-redundant columns.
A defective cell is not always a completely unusable cell, it may simply operate outside specified performance limits. For example, a cell that is not programmed after a certain number of voltage pulses may be considered defective even though it is capable of programming if additional pulses are provided. The performance limits that are chosen determine the number of defective cells that are found. By setting high performance limits, overall performance may be improved (e.g. program time may be reduced) but the number of defects will increase. Setting low performance limits reduces the number of defects at the expense of performance.
While the prior art column replacement scheme of FIGS. 1 and 2 described above allows a memory array to be operated with one or more defective cells, it has several drawbacks. This scheme requires as many redundant columns as there are non-redundant columns with defective cells, generally one redundant column per defect. Redundant columns occupy valuable space on a chip and add to the cost of producing a chip. The more redundant columns are provided, the greater the cost. However, if too few redundant columns are provided, there may not be enough redundant columns to repair some chips so that the chip is unusable. Thus, yield may suffer if too few redundant columns are provided. Newer memory arrays have more memory cells and smaller feature sizes, which tend to increase the number of defects in a memory array. Also, as more cells are programmed together in large pages, programming time tends to be limited by a few slow cells if they are not replaced. Thus, replacement of defective cells is important for newer memory systems.
Therefore, there is a need for a more space efficient way of mapping defective cells. There is also a need for memory systems that include circuitry for more efficiently carrying out such mapping.